Convolution weights are locally stored as 4-bit digital values. The circuit has been synthesized in 110 nm CMOS technology. For this configuration, the simulation results show that the circuit is able ...

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In this paper, an approximate logic synthesis (ALS) method target for circuit area reduction is proposed for adder design. The method include the approximate function description of the adder and the ...

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A novel “16 transistor” (16T) 1-bit Full adder (FA) circuit based on CMOS transmission-gate (TG) and pass transistor logics (PTL) is presented. This 1-bit FA circuit with TG and PTL structure is ...