This paper proposes the Full Adder Circuit using Multi-Input MRL without CMOS. It is designed by Multi-Input MRL which component and delay time less than 1-bit full adder circuit using Hybrid ...

A novel 1-bit hybrid full adder circuit is implemented using eighteen transistors. Simulations are done using the Cadence Virtuoso Schematic Editor in 180 and 90 nm technologies. The performances are ...