The reason for this is that moving to 12 cores in the CCD would require the normal L3 cache embedded in the chiplet to be increased to 48 MB, from the 32 MB. AMD could stick to using 64 MB for the ...

The chiplet model is gaining momentum as an alternative to developing monolithic ASIC designs, which are becoming more complex and expensive at each node. Several companies and industry groups are ...

Introducing OPENEDGES’ Universal Chiplet Interconnect Express (UCIe) Controller IP, OUC, designed to transform the semiconductor landscape with innovative multi-chiplet designs. This UCIe chiplet ...

Early Baya customers and partners include Tenstorrent, which has licensed Baya technology for its AI and RISC-V chiplet solutions, and some yet to be announced partnerships, signaling Baya’s ...

The development contract includes BOS’ s recently introduced Eagle-N (250 TOPS of automotive AI accelerator) and Eagle-A (stand-alone ADAS SoC) in the chiplet system configuration using a high-speed ...

The development of this chiplet builds on Axelera AI’s innovative approach to Digital In-Memory Computing (D-IMC) architecture, which provides near-linear scalability from the edge to the cloud.

AI hardware startup Axelera AI has unveiled its Titania AI inference chiplet. The company announced the hardware following a €61.6 million ($66.9m) grant from the EuroHPC Joint Undertaking’s (EuroHPC ...

Baya Systems says it has developed a “revolutionary” chiplet-optimized NoC and physical link or PHY interconnect solution that gets around this challenge. Though it’s possible to connect ...

EuroHPC JU DARE project accelerates development of scalable, energy efficient AI inference Titania™ chiplet for high-performance computing, data centers and more. What's new: Axelera AI ...