SANTA CLARA, Calif. — Chip-packaging giant Advanced Semiconductor Engineering Inc. (ASE) today unveiled a new wire bonding technique that reduces the die size but increases I/O for complex chips.

Developed in the 1950s, a wire bonder stitches one chip to another chip or substrate using tiny wires. Wire bonding is used for low-cost legacy packages, mid-range packages and memory die stacking.

The flip-chip package is the answer to these requirements. Up until now, the use of the wire-bonding technique has been a fundamental process in the packaging of ICs. However, as IC technology ...

Fig. 2: Flip-chip BGA package. Source: UTAC . Wire bonding, the oldest and lowest cost interconnect scheme, is performed using a wire bonder from ASM Pacific, K&S and others. Bonders are used to make ...

“X-Wire Technology will enable us to pack more chip functionality into standard packages permitting bonding wires to now touch and cross in 3D space, without risk of electrical failure.

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It enables interconnections between the die and other electronic components in an integrated circuit (IC), such as transistors and resistors. Wire bonding establishes an electrical connection between ...

Harvatek Corporation has introduced a new LED product in chip scale package (CSP). This LED has high brightness with low power dissipation and there are no wire bonding which reduces the ...

Wire Bond vs. Flip Chip In the wire bond method (top), the die faces up and is attached to the package via wires. The flip chip (bottom) ...