The voltage doubler described in this Design Idea is a modification of the Dickson charge pump. Unlike that circuit, it needs no DC input voltage, but only a digital clock whose peak value is ideally ...

So much for theory. Translation of Figure 2 into a complete voltage doubler is shown in Figure 3. Figure 3 Complete voltage doubler: 100 kHz pump clock set by R1C1, Schmidt trigger , driver (U1), and ...

STAR4003 is designed in a TSMC 40nm process with 3.3V tolerant devices. It outputs an open loop doubled voltage from the input supply. The IP integrates two NMOS power switches and two PMOS power ...

The basic voltage doubler configuration is the most common charge pump circuit. ... Clock speeds can be anywhere in the 10-kHz to 2-MHz range. If more diode and capacitors segments are added, ...

[Limpkin] has an idea for a project that uses a lot of IN-9 Nixie tubes. Where a Nixie tube clock would only use four or six tubes, [Limpkin] is looking at fifty IN-9 bar graph Nixie tubes. These t… ...

Emerging as an industry first, the Si53xx family of jitter-attenuating clock multipliers generate any output frequency from any input frequency with just 0.3 ps of jitter. The ...

It’s a voltage doubler that uses a 74HC14 logic chip. ... On the breadboard you see two chips, one is used as a clock signal generator for the other which is acting as part of the charge pump.

I'm experimenting with underclocking my athlon 1.4 to get the best combo of cooling/quietness. Obviously, I'm changing both the vcore voltage and the multiplier. Is there a website that tells me ...